1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, and more particularly relates to a method of manufacturing a semiconductor device with regard to a film thickness of a gate oxide film.
2. Description of the Related Art
There are techniques known for forming a plurality of transistors in which film thicknesses of gate oxide films are different from each other on the same substrate. For example, Japanese Laid-Open Patent Application (JP-P2005-5668A) discloses a method of manufacturing a dual gate oxide film. This conventional technique will be described below.
FIGS. 1A to 1C and FIGS. 2A to 2C are sectional views showing the method of manufacturing the dual gate oxide film, in this conventional technique. In each of the drawings, the left side indicates the region where the transistor having the thick gate oxide film is formed (hereafter, referred to as the thick film Tr region), and the right side indicates the region where the transistor having the thin gate oxide film is formed (hereafter, referred to as the thin film Tr region).
With reference to FIG. 1A, an isolation region (STI: Shallow Trench Isolation) 110 is firstly formed in a silicon substrate 101. Next, with reference to FIG. 1B, the surface of the silicon substrate 101 is oxidized to form a first gate oxide film 102 such that the first gate oxide film 102 covers the surface of the silicon substrate 101. After that, with reference to FIG. 1C, a lithography operation is used to mask the thick film Tr region with a resist 103, and the resist 103 is patterned so as to open only the thin film Tr region. Next, with reference to FIG. 2A, the first gate oxide film 102 in the thin film Tr region is wet-etched by using an acidic chemical solution. Consequently, the first gate oxide film 102 in the thin film Tr region is removed.
At this time, in the boundary between the thin film Tr region and the thick film Tr region, the chemical solution invades the interface between the resist 103 and the first gate oxide film 102. For this reason, an end 120 of the first gate oxide film 102 in the thick film Tr region is partially etched. After that, with reference to FIG. 2B, the resist 103 is removed. The end 120 of the first gate oxide film 102 in the thick film Tr region becomes thinner towards the thin film Tr region, in the boundary between the thick film Tr region and the thin film Tr region. Then, with reference to FIG. 2C, a second gate oxide film 104 is formed. Consequently, the gate oxide film having the thin film thickness, which is constituted by only the second gate oxide film 104, can be formed in the thin film Tr region. On the other hand, the gate oxide film having the thick film thickness, in which the first gate oxide film 102 and the second gate oxide film 104 are laminated, can be formed in the thick film Tr region. However, in a region P of the boundary of the thick film Tr region, the film thickness becomes thin. For this reason, since the transistor cannot be formed in this region P, this is defined as a forbidden region where the placement of the transistors is forbidden when a circuit is designed. In future, as the miniaturization of a semiconductor circuit is advanced, this forbidden region exhibits the severe influence as the new subject of the miniaturization. The technique is desired which can reduce the forbidden region in the boundary between the thin film Tr region and the thick film Tr region. The technique is desired which can attain the miniaturization of the semiconductor circuit efficiently without any waste of regions in a semiconductor chip.
In conjunction with the above technique, Japanese Laid Open Patent Application (JP-P2005-129711A) discloses a semiconductor device and a method of manufacturing the same. This method of manufacturing the semiconductor device includes: a step of forming a bottom oxide film on a semiconductor substrate of a memory transistor formation region and a peripheral circuit transistor formation region; a step of forming a nitride film on the bottom oxide film; a step of forming a top oxide film on the nitride film; a step of removing the top oxide film, the nitride film and the bottom oxide film in the peripheral circuit transistor formation region to expose the surface of the semiconductor substrate in the peripheral circuit transistor formation region; a step f executing a heat treatment in the atmosphere having nitrogen and oxygen in each of the semiconductor substrate of the peripheral circuit transistor formation region and the top oxide film of the memory transistor formation region; and a step of forming a gate insulating film on the semiconductor substrate in the peripheral circuit transistor formation region.